Systems and methods for computer initialization

ABSTRACT

Systems and methods for initializing devices such as computers, computer-based appliances, and processors and, in particular, systems and methods for initializing devices comprising one or more volatile logic devices after a power turn-on or a commanded reset. In one aspect, a method for initializing a computer system comprises sensing a command signal to boot the computer system, generating a first control signal to initialize a boot process, generating a second control signal to initialize a programmable logic device prior to completion of the initialization of the boot process, and booting the computer system using the initialized programmable logic device. In another aspect, a boot manager circuit is provided for managing initialization of a computer system. One embodiment of a boot manager circuit comprises a first sense circuit for sensing power-up and ensuring power stability, a second sense circuit for sensing a command signal to boot the computer system; a control circuit for generating a control signal in response to sensing of a command signal, to initialize a programmable logic device in advance of a boot process, and a state machine for outputting a flag indicative of the type of the type of boot process commanded.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is based on a United States provisionalapplication Serial No. 60/180,114, filed on Feb. 3, 2000, which is fullyincorporated herein by reference.

BACKGROUND

[0002] 1. Technical Field

[0003] The present invention relates generally to systems and methodsfor initializing devices such as computers, computer-based appliances,and processors and, more particularly, to systems and methods forinitializing devices comprising one or more volatile logic devices aftera power turn-on or a commanded reset.

[0004] 2. Description of Related Art

[0005] Computers and computer-based appliances, e.g. PCs (personalcomputers), PDAs (personal digital assistants) and other embeddeddevices, currently employ large, often complex, operating systems toexecute user programs and process data. Conventional operating systemstypically range in size from hundreds of kilobytes for, e.g., small PDAsto hundreds of megabytes for, e.g., high-end servers and PCs. Ascomputers and processors become embedded in increasingly more devices,the need for instant computer initialization from a power turn-on (coldboot) or commanded reset (warm boot) becomes even more highly desirable.

[0006]FIG. 1 is a block diagram of a conventional computing deviceillustrating a plurality of boot storage options. More specifically, aplurality of boot devices are shown including a magnetic hard disk 10,CD read only memory (CDROM) 20, floppy disk 30, network 40 (e.g.,wireless network), read only memory (ROM) 50, non-volatile orpre-initialized random access memory (RAM) 60, flash memory 70, or anyother non-volatile or pre-initialized volatile memory device (80). Eachof the boot devices 10-80 are interconnected by a respective interface90-160 to their respective data storage/ retrieval adapters 170-240. Ina typical legacy system as shown in FIG. 1, each storage adapter device170-240 is connected to an expansion bus 330 via respective interfaces250-320. The expansion bus 330 is connected to an expansion bus adapteror bridge adapter 340. The expansion bus 330 and expansion bus adapteror bridge adapter 340 are utilized to interconnect the storage adapterdevices 170-240 to a main bus 395 of a computer, wherein the computercomprises one or more processors 350, a main RAM storage device 360, aROM/flash memory 380, other input/output devices 390 (e.g., mousekeyboard, microphone, etc), and power-up and reset circuitry 370. Inthis conventional system, the computer reset and power-up circuitryimplements both a “cold” and a “warm” boot process as is known in theart.

[0007]FIG. 2 comprises a plurality of timing diagrams depicting aconventional “cold” boot process and a conventional “warm” boot process,which are typically implemented in the computer reset and power upcircuits 370 (FIG. 1). More specifically, the combination of FIGS. 2aand 2 b illustrate a cold boot process while FIGS. 2c, 2 d and 2 eillustrate a warm boot process. In FIG. 2a, when power is activated, thevoltage level increases from an off state to an operating voltage range420. As further illustrated in FIG. 2a, when the power is reset, apower-up reset operation is performed by momentarily asserting asystem-reset signal 410. Typically, the system-reset signal 410 tracksthe voltage rise of the power supply, with the exception of a phase lagassociated with achieving a power supply voltage threshold 420. Thepower supply voltage threshold 420 of the system-reset signal 410provides a sufficient delay of operation to ensure reliable logicoperation is achieved.

[0008] In FIG. 2a, when the system-reset signal 410 reaches thresholdvoltage 420, the system-reset signal 410 is asserted active low for aprocessor reset time period 430 (of X milliseconds), during which timean attempt is made to initialize the processor into a known reset state.For example in IBM compatible personal computers, X is approximately 200milliseconds. In FIG. 2b, a system clock preferably begins generating aprocessor clock signal 440 when (or prior to) the system-reset signal410 is asserted to initialize the processor into a known reset state. InFIG. 2a, when the system-reset signal 410 is deasserted after the timeinterval 430, the computer's boot device is required to be availableeither instantaneously or within a predetermined time period thereafter.For example, the industry standard Personal Computer Interface Bus (PCIBus) Specification Revision 2.2 requires that the boot device beavailable 5 bus clock cycles after the negation of the bus reset. With astandard PCI Bus clock frequency of 33 megahertz, the boot device mustbe available in approximately 152 nanoseconds. In particular, this isillustrated in FIG. 2b, wherein the number of clocks for the boot deviceto be available after the system-reset signal 410 (as well as signal 415for the warm boot process) is deasserted is 5 clocks. If the boot deviceis not available upon the expiration of this predetermined time, thesystem may crash or be delayed from booting.

[0009]FIG. 2c illustrates a warm boot commanded-reset-request signal 445that is generated by a commanded request, e.g., a boot request from thesystem, an application, operating system, a user, etc. Often computersincorporate a user accessible pushbutton or other switching device bywhich the user may request a warm boot. FIG. 2d illustrates asystem-reset signal 415 that is generated upon a commanded request. Thesystem-reset signal 415 is asserted for a processor reset time period431 (of X msec ) upon a commanded reset (similar to FIG., 2 a discussedabove). It should be noted that signals 410 and 415 are the same signal,except that FIGS. 2a and 2 d illustrate the different states of thesystem-reset signal upon initiation of the cold and warm boot processes.FIG. 2e illustrates the system processor clock timing (similar to FIG.2b) for the warm boot process. The boot requirements described above(e.g., processor reset time, time for boot device to be available, etc.)with respect to the cold boot process may be the same as the warm bootprocess. With the warm boot, it may be assumed that clock signal 440 isoperating prior to the system-reset signal 415 being asserted, althoughit is not necessary.

[0010]FIG. 3a is a flow diagram of the conventional power-up “cold” bootprocess. A system waits in an idle state for the power supply to beturned on (step 500). When the power is applied (affirmativedetermination in step 500) and the power supply voltage meets a presetthreshold (affirmative determination in step 510), the system-resetsignal is asserted active low for X msec (step 520). At the expirationof the time period X, the system-reset signal is deasserted (step 530).An optional maximum delay of n clock cycles (step 540) (or some otherprespecified time period) for boot device availability may be inserted.The boot process proceeds to boot the system by loading, e.g., anoperating system or application program, etc., if one or more of theassociated boot device(s) are available (step 550).

[0011]FIG. 3b is a flow diagram of a conventional “warm” boot process.When an already powered computer receives a commanded-reset-requestsignal (affirmative result in step 560), which may be received from auser, the operating system, a computer bridge, an adapter, anapplication program, etc., the system-reset signal is asserted for Xmsec (step 570). At the expiration of time period X, the system-resetsignal is deasserted (step 575). An optional maximum delay of n clockcycles (step 580) (or some other prespecified time period) for bootdevice availability may be inserted. The boot process proceeds to bootthe system by loading, e.g., an operating system or application program,etc., if one or more of the associated boot device(s) are available(step 590).

[0012] A trend within the current art of digital logic devices is theuse of volatile programmable logic components, which enable in-situconfiguration, and reconfiguration of logic. Logic devices arecontinually undergoing a technical metamorphosis. Originally, digitaldesigners implemented designs in TTL type logic devices (small-scaleintegration). These TTL type devices expanded into larger gate countsper package (medium scale integration) with alternate processtechnologies affording lower power consumption, wider voltage ranges,and specialized electrical interfaces. With the subsequent advent oflarge and then very large scale integration, embedded systems on a chipbecame a reality, with dramatically reduced costs. There are, however,various disadvantages associated with implementing dedicated very largescale systems or subsystems on a chip including, but not limited to,high non-recurring design costs, limited flexibility, inherently longfabrication times, high risk due to the time and cost for designiterations, and perhaps most importantly, lack of field upgradeability.

[0013] Consequently, manufacturers of logic devices (such as Xilinx andAlterra) have switched to field programmable logic devices to enablelogic users to program devices at the time of logic manufacturer or inthe field. To achieve very high logic densities, the current logicdevices are volatile and, thus, loose their internal logic program eachtime power is removed. For example, either a non-volatile memory deviceor a preloaded volatile memory device must be available for loading the“logic code” into the volatile logic device before the boot code (e.g.,operating system, drivers, etc.) is accessible from the boot device.Furthermore, the time needed to load the logic device can beunacceptably longer than the time allotted for a boot device to beavailable following a system reset, since many volatile fieldprogrammable gate arrays utilize serial or parallel loading modes with arelatively low or moderate bandwidths.

[0014]FIG. 4 is a block diagram of a conventional system comprising aboot device storage adapter 720 comprising a non-volatile logic device725. More specifically, the boot device storage adapter 720 employs anon-volatile logic device 725 to access boot data from a boot storagedevice 700. Data is read from the boot device 700, typically across anindustry standard interface 710, via the non-volatile logic device 725,and then onto the optional expansion bus 330, where it read by thecomputer via the optional expansion bus adapter/ bridge 340. It is to beunderstood that the boot device 700 represents any of the boot devices10-80 in FIG. 1.

[0015] In the exemplary system of FIG. 4, when the computer issues asystem-reset-signal 410/415 (for a cold boot or warm boot,respectively), and optionally generates an expansionbus-reset-signal750, the computer will attempt to load the boot data from the bootstorage device 700. If the non-volatile logic device 725 were to bereplaced by a volatile logic device, this volatile logic device mustfirst be loaded with the appropriate logic code. Thus one problemassociated within the current art is the delay associated with loading avolatile logic boot device after a power-up reset. In the best case thislengthens the boot process that, in many systems, can render theoperating system unbootable.

[0016] Another limitation within the current art is the need for loadingor reloading one or more programmable logic devices 730 upon a warm bootprocess. Often warm boots are required when a computer application oroperating system becomes unstable or corrupted. Depending on theapplication, however, a warm boot process may or may not require loadingof the volatile logic device 725 utilized in the given boot storageadapter or interface 720. These problems within the current art andother limitations are addressed by the present invention.

SUMMARY OF THE INVENTION

[0017] The present invention is directed to systems and methods forinitializing devices such as computers, computer-based appliances, andprocessors. In particular, the present invention is directed to systemsand methods for initializing devices comprising one or more volatilelogic devices after a power turn-on or a commanded reset.

[0018] In one aspect of the present invention, a method for initializinga computer system comprises the steps of: sensing a command signal toboot the computer system; generating a first control signal toinitialize a boot process; generating a second control signal toinitialize a programmable logic device prior to completion of theinitialization of the boot process; and booting the computer systemusing the initialized programmable logic device.

[0019] In another aspect, a boot manager circuit is provided formanaging initialization of a computer system. One embodiment of a bootmanager circuit comprises: a first sense circuit for sensing power-upand ensuring power stability; a second sense circuit for sensing acommand signal to boot the computer system; a control circuit forgenerating a control signal in response to sensing of a command signal,to initialize a programmable logic device in advance of a boot process;and a state machine for outputting a flag indicative of the type of thetype of boot process commanded. Preferably, the first sense circuit isemployed to ensure power supply stability prior to generating thecontrol signal for loading the programmable logic device.

[0020] In another aspect, the boot manager circuit processes an externalreset request to warm boot the system either with or without reloadingthe programmable logic device.

[0021] In yet another aspect of the present invention, the boot managercircuit is employed to simultaneously or sequentially load multipleprogrammable logic devices depending on the desired application.

[0022] In another aspect of the present invention, a system forinitializing a computer comprises: a boot storage device for storinginitialization program code for initializing a computer during a bootprocess; and a boot device adapter, operatively interfaced with the bootstorage device, for accessing the initialization program code from theboot storage device in response to a request from the computer system;wherein the boot device adapter comprises: a programmable logic device;and a boot control circuit for generating a control signal to initializethe programmable logic device in advance of the boot process.

[0023] The computer initialization system may further comprise a memorydevice for storing logic code associated with the programmable logicdevice. The memory device preferably comprises non-volatile memoryresiding on the boot device adapter, the computer system, device,appliance, or the boot device. In response to the control signal, theprogrammable logic device can self-load the logic code from the memorydevice.

[0024] In another aspect, the computer initialization system comprises adigital signal processor (DSP) that initializes the programmable logicdevice in response to the control signal. The DSP preferably resides onthe boot storage device adapter. The DSP can be connected to theprogrammable logic device through a dedicated bus of the DSP or a commonbus. The DSP retrieves logic code associated with the programmable logicdevice from a memory device residing on the boot storage device, theboot device adapter, and/or the computer system. In addition, the memorydevice may be employed to store logic code associated with the DSP.

[0025] In another aspect, the boot device may be employed to load thelogic code of a programmable logic device that is located in the bootdevice itself, in the boot device adapter or in the PC or appliance.

[0026] These and other aspects, features and advantages of the presentinvention will become apparent from the following detailed descriptionof preferred embodiments, which is to be read in connection with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027]FIG. 1 is a block diagram of conventional computer systemcomprising a plurality of representative boot devices;

[0028] FIGS. 2(a)-2(e) comprise timing diagrams that illustrateconventional “cold” and “warm” boot processes;

[0029]FIGS. 3a and 3 b comprise flow diagrams respectively illustratinga conventional “cold” boot process and “warm” boot processes;

[0030]FIG. 4 is a block diagram of a conventional initialization systemcomprising a boot device storage adapter comprising a non-volatile logicdevice;

[0031]FIG. 5 is a high-level block diagram of a boot management circuitaccording to an embodiment of the present invention;

[0032]FIG. 6 illustrates timing diagrams of a boot process according toone aspect of the present invention implementing the boot managementcircuit of FIG. 5 in a legacy computer system;

[0033]FIG. 7 illustrates timing diagrams of a boot process according toone aspect of the present invention implementing the boot managementcircuit of FIG. 5 in a non-legacy computer system;

[0034]FIGS. 8a and 8 b respectively comprise flow diagrams of a “cold”and “warm” boot process according to one aspect of the presentinvention;

[0035]FIG. 9 is a schematic diagram of a boot management circuitaccording to an embodiment of the present invention;

[0036]FIG. 10 is a timing diagram illustrating the waveforms at variousnodes in the diagram of FIG. 9;

[0037]FIG. 11 is a block diagram of an initialization system accordingto an embodiment of present invention utilizing a boot managementcircuit;

[0038]FIG. 12 is a block diagram of an initialization system accordingto another embodiment of present invention;

[0039]FIG. 13 is a block diagram of an initialization system accordingto another embodiment of present invention;

[0040]FIG. 14 is a block diagram of an initialization system accordingto another embodiment of present invention;

[0041]FIG. 15 is a block diagram of an initialization system accordingto another embodiment of present invention; and

[0042]FIG. 16 is a block diagram of an initialization system accordingto another embodiment of present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0043] The present invention is directed to systems and methods forinitializing devices such as computers, computer appliances, andprocessors. More specifically, the present invention is directed tosystem and methods for initializing (programming) a volatileprogrammable logic device (employed in the computer or processor bootprocess) in advance of its application. In the following description, itis to be understood that system elements having equivalent or similarfunctionality are designated with the same reference numerals in theFigures. The systems and methods described herein may be implemented invarious forms of hardware, software, firmware, or a combination thereof.Preferably, the present invention is implemented utilizing a combinationof novel analog signal processing techniques and digital logic appliedto programmable logic technologies, high density non-volatile storagedevices, digital signal processors or any other type of processingdevice or technique. Additionally, the present invention is applicableto any type of programmable logic device utilized in the boot process ofa computer or appliance, which is utilized to load the operating system,drivers, application code, or any other software and firmware.

[0044]FIG. 5 illustrates a high-level block diagram of a boot managementcircuit 1070 according to an embodiment of the present invention. Ingeneral, a preferred architecture of the boot management circuit 1070comprises a component for sensing power-up and user/system commandedreset requests and a component for generating control signals inresponse to such power-up and commanded requests for causing logic codeto be loaded into one or more programmable logic devices in advance ofuse of such programmable logic devices in a boot process. Furthermore, apreferred boot management circuit comprises a component for determiningthe type of boot process that was initiated (e.g., power-up or commandedreset) and providing an indication of such boot process.

[0045] The exemplary boot management circuit 1070 of FIG. 5 comprises aplurality of inputs for receiving a power-supply-monitoring signal 400,an optional system-cold-boot-reset-request signal 740, an optionalcommanded-warm-boot-reset-request signal 760, (optionally) a legacysystem-reset signal 410/415; and optionally an expansionbus-reset-signal750.

[0046] In future system implementations (i.e. non-legacy) utilizing thepresent invention, a preferred implementation is to employ either thepower-supply-monitoring signal 400 and/or thesystem-cold-boot-reset-request signal 740 for determining cold bootrequests. Similarly the commanded-warm-boot-reset-request signal 760 isutilized to sense warm boot requests.

[0047] In existing (i.e., legacy) computer architectures, signals suchas 740 and 760 are typically not available from the currenthardware/software implementation, thus only existent signals must beutilized that are generated by the computer or expansion bus. Hence,preferably, for implementations within a legacy system, thepower-supply-monitoring signal 400 coupled to either the power supply orthe expansion bus power is utilized in conjunction with either anexpansionbus-bus-reset signal 750 or the system-reset signal 410/415 todistinguish between a cold and warm boot. It should be noted that inlegacy systems, the expansionbus-bus-reset signal 750 is typicallyderived from the system-reset signal 410/415, usually with appropriatebuffering or some other form of signal conditioning. Thus, when the bootmanagement circuit 1070 is implemented in a legacy system, thesystem-reset signal 410/415 or expansionbus-bus-reset signal 750 ispreferably monitored along with power-supply-monitoring signal 400. Ifthe system-reset signal 410/415 or the expansionbus-bus-reset signal 750is asserted and the power-supply-monitoring signal 400 is above thespecified threshold 420 (deemed power supply valid), then the bootprocess is a warm boot. However, if the system-reset signal 410/415 orthe expansionbus-bus-reset signal 750 is asserted and thepower-supply-monitoring signal 400 is below the specified threshold 420(deemed power supply invalid), then the boot process is a cold boot.

[0048] The exemplary boot management circuit 1070 further comprises aplurality of output pins for outputting a boot-device-reset signal 1030,a system-reset signal 410/415 (depending if a cold or warm boot processis initiated), and (optionally) indicator signals such as awarm-boot-flag indicator 1050 and/or a cold-boot-flag indicator 1040.

[0049] For non-legacy systems, it may be advantageous to generate theoptional system-reset signal 410/415 signal from the logical OR of thesystem-cold-boot-system-reset-request 740 and thecommanded-warm-boot-reset-request 760 to minimize logic circuitry. Inthe case of non-legacy systems the system-reset 410/415 is not an inputto the boot management circuit 1070 but is an output generated by theboot management circuit 1070. The non-legacy use of the system-reset410/415 is similar to its use in legacy systems where the signal 410/415may be utilized to reset processors, peripherals, and all othernon-volatile elements of the boot device. For non-legacy systems thewarm-boot-flag signal 1050 and the cold-bootflag-signal 1040 may bederived from their respective input request signals 760 and 740. Forlegacy systems the previously specified logic is preferably applied.

[0050] It is to be appreciated that the boot management circuit 1070according to the present invention can be readily employed in allexisting and future platform architectures. As such, it is to be furtherunderstood that the input signals 400, 740, 760, 410/415 and 750 andoutput signals 1030, 410/415, 1050 and 1040 are labeled with names thatdescribe their associated functions, and that, depending on theplatform, system or application, other signals providing correspondingfunctions of the signals depicted in FIG. 5 may be applied.

[0051] It is to be further appreciated that the boot-device-reset output1030 provides a mechanism for initiating the loading of the programmablelogic device in advance of the use of the programmable logic device inthe boot process. The cold-boot-flag output signal 1040, and thewarm-boot-flag output signal 1050 indicate which type boot process hasbeen commanded. Advantageously, the output flags 1040, 1050 provide anindication that allows additional logic that is implemented in eitherhardware, software, or any combination thereof, to elect to either loador reload program code in the programmable logic device, or leave intactthe current programming of the programmable logic device. Indeed,depending on the application, it may or may not be advantageous toreload the programmable logic devices. The system-reset output 410/415,typically resets either all or a portion of the PC components, appliancecomponents, or system components.

[0052] It should be noted that while singular input signals are shown,the input signals are indicative of a signal type and may each occur inpluralities. For example, the power-supply-monitoring signal 400 maycomprise a plurality of power senses. Typically, the individual sensesthat may be utilized include +5 volts, +3.3 volts, +1.8 volts, +1.5volts, +12 volts, and −12 volts, although any suitable voltage orcombination thereof may be implemented. The power-supply-monitoringsignal 400 may be monitored and logically combined using any suitableconventional logic equation to provide a power sense. Certain powersupply voltages are used for specific functions. For example +5 and +3.3volts may be utilized for logic input and output while lower voltagessuch as +1.5 volts may be utilized for internal logic cores ofhigh-density logic devices and processors. The process of monitoringvoltages is application specific to a number of parameters including thespecific logic implementation, system functionality, and/or processorsutilized in the computer or appliance. Further, the ordering may besensed to ensure that the power has been applied in the proper sequence,i.e., the logic cores are powered before I/O devices to avoid latchup).

[0053] Referring now to FIG. 6, a plurality of timing diagrams are showndepicting both cold and warm boot process for implementation of the bootmanagement circuit 1070 in a legacy system. In FIG. 6(a), upon power-upof the system, a power-supply-monitoring signal 400 reaches a stable andacceptable voltage operating range 405 within a given time period. Thephase lag associated with the power-supply-monitoring signal 400 mayvary based upon factors such as the source impedance and load conditionof the input source and the internal functioning of the power supply,topology, analog or switching, frequency of switching, capacity, etc.Then, as illustrated in FIG. 6(b) (which is similar to FIG. 2(a)), thesystem-reset signal 410 for a cold boot is generated, which typicallyapproximates the power-supply-monitoring signal 400 until a minimumthreshold voltage 420 is reached so as to enable proper logic operation.Once the threshold 420 is reached, (with a cold boot process), thesystem-reset signal 410 is asserted for X milliseconds. Although thetime period X is typically 200 milliseconds, any suitable value for Xmay be implemented in the present invention, as the present invention isnot specific to any given value. Indeed, it is anticipated that thistime period with grow smaller in future systems. Additionally, it is notrequired that the system-reset signal 410 follow thepower-supply-monitoring signal 400. Indeed, the system- reset signal 410may remain continuously asserted until it is negated.

[0054] For a warm boot process, in FIG. 6(c)(which is similar to FIG.2(d), the system-reset signal 415 is asserted for Y milliseconds,wherein Y may be any suitable time period. It is to be understood thatnotwithstanding that FIG. 7 illustrates that X=Y, their values may bedifferent depending on the application. For instance, warm bootprocesses may benefit from a reduced time Y since certain systemelements may not require initialization or since there are lesstransients within a system that is already powered (pre-chargedcapacitances and inductances).

[0055] In FIG. 6(d) (which is similar to FIG. 2(b)), the systemprocessor clock generates the clock signal 440, which typically beginsoperation once the input power has reached an acceptable operatinglevel. While it is possible that the system clock is held in reset untilthe system-reset signal 410/415 is negated, it is often preferable toallow the system clock 440 to operate during the time interval X, (or Yto aid the system logic and/or initializing the processor into a knownstate. For example, many general-purpose processors and digital signalprocessors typically require a number of input clocks to properlyoperate when released from the reset state. It is to be understood thatthe system processor clock signal 440 is shown for pedagogical purposesand is not a required element of the present invention. Again, a maximumdelay from reset negation to boot device availability may be implementedbased on, e.g., a maximum number n of clock cycles (or some otherprespecified time interval). For example, in the Personal ComputerInterface Specification Revision 2.2, the boot device must be available5 clock cycles after the negation of reset on the bus, or the system maycrash. At the current system clock rates of 33 and 66 megahertz, thisapproximately corresponds to maximum times of 150 and 75 nanoseconds,respectively. Again, the maximum delay from reset negation to bootdevice availability may be anywhere from zero to some maximum specifiedtime value delineated in any convenient units including multiples ofclock periods.

[0056] As further illustrated in FIG. 6(e), in a cold boot process, theboot-device-reset signal 1030 preferably follows thepower-supply-monitoring signal 400, although this is not essential forimplementing a boot process according to this invention. With a warmboot process, the boot-device-reset signal 1030 will change from anegated state to an asserted state upon the system-reset-signal 415being asserted. When the system-reset signal 410 is asserted to activelow, the boot-device-reset signal 1030 is asserted to active low for Zmsec, where Z comprises a number that is shorter than the respective Xor Y time periods for cold and warm boots respectively. In general, theperiod of time X−Z (or Y−Z with a warm boot) should be sufficient toload and activate the programmable logic device elements necessary forboot, which may comprise of a portion of one programmable logic deviceor one or more programmable logic devices. This time period may beshortened, for instance when reloading of the volatile logic device isnot necessary.

[0057] Further, an optional internal state machine is set to provide anindication of the mechanism that is responsible for initiating the bootprocess. Preferably, this mechanism comprises either asserting ornegating the cold-boot-flag 1040 along with the complementarywarm-boot-flag 1050. In particular, as shown in FIGS. 6(f) and (g), in apreferred embodiment, the signals 1040, 1050 change state when theboot-device-reset signal 1030 is negated. It is to be appreciated thatin other embodiments of the present invention, the state machine andindicator signals may be valid earlier than negation of theboot-device-reset signal 1030, if so desired.

[0058] Referring now to FIG. 7, a plurality of timing diagrams are showndepicting both cold and warm boot process for implementation of the bootmanagement circuit 1070 in a non-legacy system. These timing diagramsare similar to the corresponding timing diagrams of FIG. 6, expect thatin FIG. 7, the system-cold-boot-reset-request signal 740 in FIG. 7(e)and the commanded-warm-boot-reset-request 760 signal in FIG. 7(f) areutilized directly as the cold and warm boot requests, as opposed totheir derivation in legacy applications as described herein.

[0059] Referring now to FIGS. 8a and 8 b, flow diagrams respectfullyillustrate a “cold” and “warm” boot process according to one aspect ofthe present invention. More specifically, with a preferred cold bootprocess as illustrated in FIG. 8a, a test or other check is continuouslyperformed to determine whether the power supply has been turned on (step500). If power has been applied (affirmative determination in step 500),a determination is then made as to whether as to whether the voltage,current, and/or aggregate power from one or more supply voltages has meta predetermined threshold (step 510). Furthermore, in the case ofunderdamped or critically damped supplies, it may also be desirable totest both high and low voltage rails to ensure that the power supply hassettled. This process may also include a time delay to ensure that thesupply is not in the process of oscillating above and below thethresholds, inducing a false power supply valid indication. Multiplesenses (and the order thereof) may be combined to derive the mostreliable or otherwise optimal indication of power supply validity, if sodesired.

[0060] Upon power supply validity (affirmative determination in step510), preferably, two parallel processes occur (i.e., a first parallelprocess comprising steps 520, 530 and 540, and a second parallel processcomprising steps 1200, 1210, 1220 and 1230). More specifically, thefirst parallel process initiates with the system-reset signal 410 beingasserted for X msec (step 520), or some other prespecified time period.Then, after expiration of the time period X, the system-reset signal 410is deasserted (step 530). Then, a time delay 540 (shown in FIG. 7(n) asn clock cycles) is optionally inserted before the boot process 550begins.

[0061] In the second parallel process, the boot-device-reset signal 1030is asserted (substantially concurrently with the assertion of thesystem-reset signal 410) for Z msec (step 1200), wherein Z<X. During thetime period Z, any logic devices utilized on the boot storage adapter orprocessors may be reset including those utilized to load the volatilelogic device including the boot storage device. At the expiration of Z,the boot-device-reset signal 1030 is deasserted (step 1210). Then, theboot state indicator is optionally read to ensure the appropriate bootprocess and loading of the correct logic code into the programmablelogic device (step 1220). Next, the programmable logic device is loaded(step 1230). It is to be noted that a delay may then be encounteredwaiting for completion of the first parallel process. Finally, the bootprocess begins (step 550).

[0062] With a preferred “warm” boot process as depicted in FIG. 8b, atest or other check is continuously performed to determine whether arequest for reset (e.g., user, system, application, etc.) has beenasserted (step 560). If so (affirmative determination in step 560), twoparallel processes occur (a first parallel process comprising steps 520,530, and 580, and a second parallel process comprising steps 1200, 1210,1220, and 1230). The first parallel process initiates with system-resetsignal 415 (master reset) being asserted active low for time period of Ymsec (step 520), wherein Y may be equal to any suitable time period.After the system-reset signal 415 has been asserted for the prespecifiedtime period Y, the system-reset signal 415 is deasserted (step 530) anda maximum time delay of n clock cycles is optionally mandated (step 580)for the availability of the boot device. The boot process begins (step590) if the boot device is available.

[0063] In the second parallel processes, the boot-device-reset signal1030 is asserted for Z msec (step 1200), wherein Z<Y. After theexpiration of Y, the boot-device-reset signal 1030 is deasserted (step1210). Then, the boot state indicator is optionally read to ensure theappropriate boot process and loading of the correct logic code into theprogrammable logic device (step 1220). Next, the programmable logicdevice is loaded (step 1230). It is to be noted that a delay may then beencountered waiting for completion of the first process. Finally, theboot process begins (step 590).

[0064]FIG. 9 illustrates a schematic circuit diagram of a bootmanagement circuit 1070 (FIG. 5) according to a preferred embodiment ofthe present invention. In the illustrated embodiment, the bootmanagement circuit 1070 comprises a power supply sense circuit 1071comprising an input node A, a diode D1, resistors R1 and R4, a capacitorC1, a jumper J1 and output node B. Preferably, R1 is at least one orderof magnitude lower than the resistance R4. The power sense circuit 1071is essentially a dual time constant integrator with R4 and C1 definingthe charge time constant and R1 and C1 defining the discharge timeconstant. While it is preferable that D1 have a low forward bias voltagesuch as those found in Schottky diodes, it is not necessary as R4 bleedsout residual charge at a low rate for voltages below and the forwardbias of the diode D1 when the power supply sense voltage (at node A)drops below the forward bias of the diode D1.

[0065] The jumper J1 may be used to short-circuit the other componentsof the circuit 1071 to eliminate the effect of the charge/discharge timeconstants in the event that the power supply provides the neededcharacteristics.

[0066] The boot management circuit 1070 further comprises a Schmidtinverter U1, operatively connected to the power sensor circuit 1071 atnode B, and operatively connected to an input of a falling edgedifferentiator 1072 at node C. The falling edge differentiator 1072preferably comprises a capacitor C2 and resistor R2. The inverter U1 isemployed in conjunction with the falling edge differentiator 1072 togenerate a pulse (at node D) that is utilized to create aboot-device-reset signal 1030 (at node E) by means of a two inputSchmidt AND gate U2 (which operates as an active low in, active low out,OR gate).

[0067] The boot manager 1070 further comprises a system reset circuit1073 comprising a jumper J2 and resistor R5, for processing the legacysystem-reset signal 410/415, a jumper J3 again with resistor R5, forprocessing the expansionbus-bus-rest signal 750, and a jumper J4 andresistor R6 for processing the commanded-warm-boot-reset-request signal760 (which are discussed above with reference to FIG. 5). By inclusionof jumpers J2, J3, or J4, and an appropriately asserted reset-requestsignal at the respective input, a boot-device-reset signal 1030 (at nodeE) will be generated. It should be noted that each of the jumpers J1-J4illustrated in FIG. 9 may comprise any suitable conventional switchingdevice, including, but not limited to, passive or active, or static ordynamic, switching devices. When jumpers J2, J3 and J4 are notinstalled, resistors R5 and R6 are utilized as logic pull-ups to defaultthe system and external reset requests to the inactive state.

[0068] Next, an AND gate U3 is utilized to combine the system and userreset request signals into one combined request (output at node H). Adifferentiator circuit 1074, comprising a capacitor C3 and a resistorR3, acts as a rising edge differentiator whose output (at node I) isthen supplied to a Schmidt inverter U4 for waveshaping the reset requestpulse (output to node J). It is to be noted that the values of C3 and R3are preferably selected based on the desired pulse width time of thesignal output at node J. U2 is again utilized to logically OR thepower-up system reset, and external reset request. An S/R flip-flop U6implements a state machine that asserts and negates the appropriatewarm-boot and cold boot flags, 1050, 1040. A Schmidt inverter U5 isutilized to convert the polarity of the power-up reset for appropriateoperation of the state machine. As previously noted, the ability for acomputer or computer appliance to inquire about the boot initiator isadvantageous, as it provides a mechanism for rebooting of only thosesystem and reloading of those programmable logic devices that arerequired or desired.

[0069]FIG. 10 comprises a plurality of timing diagrams illustrating thestate of the signals located at each node (A-J) of the boot managercircuit illustrated in FIG. 9. More specifically, the letterdesignations A-J correspond to the waveforms generated as a function oftime at the associated nodes labeled in the schematic diagram of FIG. 9.Signal A illustrates a typical turn-on transient of a power supply of acomputer or computer appliance. With computers comprising low costswitching power supplies that operate with the power consumption ofhundred of watts, this time is typically 5 msecs. This time and theactual profile vary significantly based on the design and individualsystem tolerances. It is expected that as power supplies continue tobecome more efficient and faster, the switching frequencies willincrease causing a shorter turn on profile. The present embodiment doesnot rely on any specified time or wave shape for the turn on profile.

[0070] Further, Signal B depicts the voltage waveform input to U1 asgenerated by Signal A (power supply sense input) charging the Cl withtime constant R4C1. The Schmidt trigger U1 provides thresholdhysteresis, affording a higher level of nose immunity. It is to be notedthat U1 is not a necessary component of the invention.

[0071] Signal C is the output of the Schmidt trigger inverter U1, andSignal D is the output as processed the differentiator circuit 1072.Signal D is input to the Schmidt AND gate U2 to generate theboot-device-reset signal 1030 as illustrated Signal E. Signal D is alsoinput to the Schmidt inverter U5, which outputs Signal K. Signal K isinput to S/R flip-flop U6 which then sets the indicator cold-boot-flag1040 shown as Signal L. The complementary output indicatorwarm-boot-flag 1050 is simultaneously negated as shown Signal M.

[0072] The system-reset signal 410/415 andcommanded-warm-boot-reset-request signal 760 are shown disabled by theremoval of jumpers J2 and J4, respectively. Both requests are shownactive low and Signals F OR G show individual requests. The Schmidt ANDgate U3 logically ORs the request and generates Signal H as an input tothe rising edge differentiator circuit 1074. The output of thedifferentiator circuit 1074, Signal I, is the input to Schmidt inverterU4 which generates signal J that is input to both U2 and U6.

[0073] A boot-device-reset signal 1030 is then generated and the S/Rflip-flop U6 is set to the cold-boot-flag 1050 as indicated by Signal M.As before, the use of Schmidt function provides additional noise marginthrough the logic's hysterisis and is optional to all logic functions inthe present invention.

[0074]FIG. 11 is a block diagram of a boot management system accordingto an embodiment of present invention utilizing a local non-volatilestorage device and volatile logic device. A boot storage device 700stores an operating system and/or application programs, which are to beloaded upon system initialization. The boot storage device 700 maycomprise any mass storage device. An optional interface 710 operativelyconnects the boot storage device 700 to a boot device storage adapter770 (although the boot storage device may be directly connected to acomputer, computer appliance, processor, etc). The boot device storageadapter 770 comprises a volatile logic device 730 that is implemented toaccess the boot storage device 700 and/or process operation of the bootstorage device 700. The boot device storage adapter 770 furthercomprises a non-volatile logic device 736,which stores the logic programfor the volatile logic device 730. As indicated above with reference toFIG. 5, a boot management circuit 1070 (incorporating one embodiment ofthe present invention) receives boot requests from apower-supply-monitoring signal 400, an optionalsystem-cold-boot-reset-request signal 740, acommanded-warm-boot-reset-request signal 760, (optionally) a legacysystem-reset signal 410/415, and (optionally) an expansionbus-resetsignal 750.

[0075] Advantageously, as indicated above, the boot management circuit1070 ensures that the volatile logic device 730 is preprogrammed andoperational prior to a request from the external adapter/bridge 340 (orthe PC/appliance itself) to access, or receive data from the bootstorage device 700. It is to be appreciated that as explained above, theboot management circuit 1070 is readily backwards compatible with legacysystems because the boot management processes and converts boot signalsof legacy systems into signals that are used for implementing thebooting techniques described herein. It is to be further appreciatedthat the methods and systems described herein may be implemented inlegacy free systems.

[0076] The volatile logic device 730 may utilize a conventionalself-loading mechanism to load its associated logic code in response toa control signal from the boot management circuit Alternatively, thelogic code for the volatile logic device can be loaded by means ofexternal logic circuitry. It should be noted that within the currentart, boot storage devices may be addressed as memory or mass storagedevices. Further, the access to the boot storage device 700 may be as aslave or the device 700 may be a master initiating the transfer itself.

[0077] Further it should be noted that in FIG. 11 thepower-supply-monitoring-signal 400 is shown operatively sensing one ormore voltages from the expansion bus as is typical in legacyimplementations. This signal may also be coupled to the power supply asin non-legacy implementations.

[0078]FIG. 12 is a block diagram of a boot management system accordingto another embodiment of the present invention, wherein a boot devicestorage adapter 771 comprises a digital signal processor or any otherprocessor 1320 and (optionally) a RAM 1330. In this embodiment, thenon-volatile memory device 736 may store the program(s) for the volatilelogic device 730 and the programs for the digital signal processor(s)1320. Also, the digital signal processor 1320, volatile logic device730, and non-volatile memory device 736 and RAM 1330 may be operativelyconnected to the volatile logic device 730 via a common bus structure1340 (although they may be connected via dedicated pathways, or anycombination of dedicated and common buses). The non-volatile memory 736may be contained within the digital signal processor 1320 or any otherelement of the current embodiment, i.e., the volatile logic device 730itself, bus adapter 340, or frontside bus 395. To load the volatilelogic device 730, the device 730 may utilize a conventional self-loadingmechanism, external logic circuitry, or the digital signal processor1320 via a common or dedicated pathway.

[0079]FIG. 13 is a block diagram of a boot management system accordingto another embodiment of the present invention. The system includes ofone or more non-volatile devices 795, 785, 796 that are remotely locatedfrom the boot device adapter 772.. For example, as specificallyillustrated in FIG. 13, a non-volatile memory device 795 may be remotelylocated on the external expansion bus 330 of the expansion bus adapter340. In addition to, or alternatively, a non-volatile memory device 785may be remotely located on the local or frontend bus 395. It is to beappreciated that a non-volatile memory device 795 and/or 785 may belocated in multiple locations either in part, or in whole, and eachnon-volatile memory device 795 and/or 785 may be dedicated to theprogrammable logic device 730 or shared for other functions. Further, itis to be appreciated that the non-volatile logic code may be locatedwithin the boot storage device itself 796 and bootstrap loaded into thevolatile logic device 730. In this embodiment, the boot device 700 maybe utilized to load the appropriate programming code into a programmablelogic device 730 located in the boot device adapter 772, or aprogrammable logic device located in the boot device 700 itself, or inthe PC or computer appliance.

[0080]FIG. 14 is a block diagram of a boot management system accordingto another embodiment of the present invention. The architecture of theboot device storage adapter 773 comprises a digital signal processor1320 (or other processor) having a dedicated input/output bus 1350 thatis utilized for programmable device loading. The addition of one or moredigital signal processors 1320 or other processor is utilized on theboot storage device adapter 773 with optional RAM 1330. The non-volatilememory device 736 may store both the volatile logic device program, andprograms for the for the digital signal processor(s) 1320.

[0081] A dedicated pathway 1350 (parallel programming bus) is shownbetween the digital signal processor(s) 1320 to the volatile logicdevice 730, which may be used for express loading the volatile logicdevice 730. A common bus 1340 is utilized for accessing the non-volatilememory device 736. In the case of a DSP 1320, bus 1340 is often referredto as the main bus and bus 1350 the I/O or expansion bus. In thisembodiment, any combination of dedicated/common busses is permissible,depending on the application. Further, the digital signal processor 1320may share the dedicated input/output bus 1350 for any purpose includingspecial purpose functions. For example, the Texas Instruments C62x andC64x family of digital signal processors has a dedicated bus forconnection to one or more industry standard T1/E1 telecommunicationsports. The signals transmitted on bus 1350 in their current format, orwhen enabled for general purpose I/O, may be utilized for programmingthe non-volatile memory device 736. Indeed, both data and strobe signalsmay be generated along with feedback for reading programming status asrequired. By using any suitable multiplexing techniques, the port mayalso be used for T1/E1 functions, thereby saving logic and cost.

[0082] A translation software program may be utilized to orient thelogic program for optimal storage and access in the non-volatile memorydevice 736, thereby saving processor cycles and minimizing the time forprogramming the volatile logic device 730. The translation programprecomputes the optimal storage patterns for the volatile logic program.The non-volatile memory device 736 may be stored in the digital signalprocessor 1320, or any other element such as the volatile logic device730, bus adapter 340 located on frontside bus 395.

[0083]FIG. 15 is a block diagram of a boot management system accordingto another embodiment of the present invention comprising a boot storagedevice adapter 774 comprising a plurality of programmable volatile logicdevices 1350, 1360. The non-volatile memory device 736 may be utilizedto store the programs of one or more volatile memory devices 1350, 1360.It should be noted that although two volatile memory devices are shown,the system may employ more than two volatile memory devices. Inaddition, although one non-volatile memory device 736 is shown, thesystem may comprise a plurality of non-volatile memory devices.

[0084]FIG. 16 is a block diagram of a computer initialization systemaccording to another embodiment of the present invention comprising aboot storage device adapter 775 comprising a plurality of volatile logicdevices and digital signal processors (or other processors). Here,separate independent dedicated pathways are utilized to load volatilelogic devices. Additionally, the outputs of the boot management circuit1070 are shown for use with other elements of the computer or appliance.

[0085] As shown in FIGS. 11-16, the non-volatile logic device 736 may beeither self-loading or loaded by an external logic device. For example,in FIG. 11, the non-volatile logic device 736 is connected to thevolatile logic device 730, which allows the volatile logic device 730 tooptionally be self-loading. In FIG. 12, for example, the non-volatilememory device 736 is connected to the DSP 1320 and the volatile logicdevice 730 has the option of being loaded by the DSP or beingself-loaded.

[0086] Although illustrative embodiments have been described herein withreference to the accompanying drawings, it is to be understood that thepresent invention is not limited to those precise embodiments, and thatvarious other changes and modifications may be affected therein by oneskilled in the art without departing from the scope or spirit of theinvention. All such changes and modifications are intended to beincluded within the scope of the invention as defined by the appendedclaims.

What is claimed is:
 1. A method for initializing a computer system,comprising the steps of: sensing a command signal to boot the computersystem; generating a first control signal to initialize a boot process;generating a second control signal to initialize a programmable logicdevice prior to completion of the initialization of the boot process;and booting the computer system using the initialized programmable logicdevice.
 2. The method of claim 1 , wherein the second control signalcauses the programmable logic device to self-load logic code from amemory device.
 3. The method of claim 1 , wherein the second controlsignal causes a logic device to load logic code into the programmablelogic device.
 4. The method of claim 1 , further comprising the step ofsensing power to ensure power stability prior to generating the secondcontrol signal.
 5. The method of claim 1 wherein the method steps areperformed by a boot management circuit that manages the boot process. 6.The method of claim 1 , further comprising the steps of generating athird control signal to indicate the type of boot process commanded. 7.The method of claim 6 , wherein the type of boot process comprises oneof a cold boot and a warm boot.
 8. A program storage device readable bya machine, tangibly embodying a program of instructions executable bythe machine to perform method steps for initializing a computer system,the method steps comprising: sensing a command signal to boot thecomputer system; generating a first control signal to initialize a bootprocess; generating a second control signal to initialize a programmablelogic device prior to completion of the initialization of the bootprocess; and booting the computer system using the initializedprogrammable logic device.
 9. The program storage device of claim 8 ,wherein the second control signal causes the programmable logic deviceto self-load logic code from a memory device.
 10. The program storagedevice of claim 8 , wherein the second control signal causes a logicdevice to load logic code into the programmable logic device.
 11. Theprogram storage device of claim 8 , further comprising instructions forsensing power to ensure power stability prior to generating the secondcontrol signal.
 12. The program storage device of claim 8 , furthercomprising instructions for generating a third control signal toindicate the type of boot process commanded.
 13. The program storagedevice of claim 12 , wherein the type of boot process comprises one of acold boot and a warm boot.
 14. A circuit for managing initialization ofa computer system, comprising: a first sense circuit for sensingpower-up and ensuring power stability; a second sense circuit forsensing a command signal to boot the computer system; a control circuitfor generating a control signal in response to sensing of a commandsignal, to initialize a programmable logic device in advance of a bootprocess; and a state machine for outputting a flag indicative of thetype of the type of boot process commanded.
 15. The circuit of claim 14, further comprising a first waveshaping circuit, operatively coupled tothe first sense circuit, for generating a first pulse signal that isutilized to generate the control signal in response to a cold bootcommand.
 16. The circuit of claim 15 , wherein the first waveshapingcircuit comprises a falling edge differentiator circuit.
 17. The circuitof claim 14 , further comprising a second waveshaping circuit,operatively coupled to the second sense circuit, for generating a secondpulse signal that is utilized to generate the control signal in responseto a warn boot command.
 18. The circuit of claim 17 , wherein the secondwaveshaping circuit comprises a rising edge differentiator circuit. 19.A system for initializing a computer, comprising: a boot storage devicefor storing initialization program code for initializing a computerduring a boot process; and a boot device adapter, operatively interfacedwith the boot storage device, for accessing the initialization programcode from the boot storage device in response to a request from thecomputer system; wherein the boot device adapter comprises: aprogrammable logic device; and a boot control circuit for generating acontrol signal to initialize the programmable logic device in advance ofthe boot process.
 20. The system of claim 19 , further comprising amemory device for storing logic code associated with the programmablelogic device.
 21. The system of claim 20 , wherein the memory deviceresides in one of the boot device adapter, the computer system and both.22. The system of claim 20 , wherein the programmable logic deviceself-loads the logic code from the memory device in response to thecontrol signal.
 23. The system of claim 22 , wherein the logic codecomprises non-volatile logic code residing in memory on the boot storagedevice.
 24. The system of claim 19 , further comprising a digital signalprocessor (DSP) that initializes the programmable logic device inresponse to the control signal.
 25. The system of claim 24 , wherein theboot control circuit comprises a state machine that outputs a flagsignal indicative of the type of boot process commanded.
 26. The systemof claim 24 , wherein the DSP processes the flag signal to determinewhether to re-initialize the programmable logic device, if the flagsignal indicates a warm boot process.
 27. The system of claim 24 ,wherein the DSP resides on the boot device adapter.
 28. The system ofclaim 24 , wherein the DSP is operatively connected to the programmablelogic device through a dedicated bus of the DSP.
 29. The system of claim28 , wherein the dedicated bus comprises a communications port.
 30. Thesystem of claim 24 , wherein the DSP retrieves logic code associatedwith the programmable logic device from a memory device residing on theboot device adapter.
 31. The system of claim 30 , wherein the memorydevice stores logic code associated with the DSP.